Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure

ABSTRACT

Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. application Ser. No. 16/215,899, filed Dec. 11, 2018, which claims the benefit of Korean Patent Application No. 10-2018-0086013, filed on Jul. 24, 2018, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference.

BACKGROUND 1. Field

The present disclosure relates to an interconnect structure, and more particularly, to an interconnect structure including a cap layer made of nanocrystalline graphene and/or an electronic device including the interconnect structure.

2. Description of Related Art

In recent years, the size of semiconductor devices is gradually decreasing for the high integration of semiconductor devices and the line width of copper wiring in an interconnect structure is reducing. Meanwhile, when the line width of the copper wiring is reduced, current density in the copper wiring is increased, and as a result, resistance of the copper wiring increases. The increase in the resistance of the copper wiring may cause electromigration of copper atoms, resulting in defects in the copper wiring. Therefore, in order to lower the resistance of the copper wiring and limit and/or prevent the electromigration, a cap layer capable of improving electromigration resistance in the copper wiring may be needed.

SUMMARY

Provided are an interconnect structure including a cap layer made of nanocrystalline graphene and an electronic device including the interconnect structure.

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

According to an aspect of an embodiment, an interconnect structure includes: a dielectric layer including at least one trench; a conductive wiring filling an inside of the at least one trench; and a cap layer on at least one surface of the conductive wiring, the cap layer including nanocrystalline graphene, the nanocrystalline graphene including nano-sized crystals.

The conductive wiring may include one of a metal, a metal alloy, and a combination thereof.

The metal may include at least one of Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, Rh, Ir, Pd, and Os.

The interconnect structure may include a barrier layer provided on the conductive wiring within the at least one trench.

The barrier layer may include a metal, a metal alloy, or metal nitride, or nanocrystalline graphene, and may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked.

The barrier layer may include Ta, Ti, Ru, RuTa, IrTa, W, TaN, TiN, RuN, IrTaN, TiSiN, Co, Mn, MnO, or WN.

The conductive wiring may include a platinum metal, and the barrier layer may include a metal having a standard oxidation-reduction potential of 0 or less.

The barrier layer may be provided on both sides and the bottom of the conductive wiring.

The barrier layer may be provided to surround the conductive wiring.

The cap layer may be provided on the top of the conductive wiring.

The cap layer may be provided on the bottom of the conductive wiring.

The cap layer may be provided on the both sides of the conductive wiring.

The cap layer may be provided on the top and the both sides of the conductive wiring.

The cap layer may be provided to surround the conductive wiring.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects will become apparent and more readily appreciated from the following description of some example embodiments, taken in conjunction with the accompanying drawings in which:

FIG. 1 is a view of an electronic device including an interconnect structure according to an example embodiment;

FIG. 2A is an example view of a Raman spectrum representing typical crystalline graphene;

FIG. 2B is an example view of a Raman spectrum representing nanocrystalline graphene according to an example embodiment;

FIG. 2C is an example view of a Raman spectrum representing an amorphous carbon layer;

FIGS. 3A to 3C are example views of a method of manufacturing an electronic device including the interconnect structure shown in FIG. 1;

FIG. 4 is a view of an electronic device including an interconnect structure according to another example embodiment;

FIG. 5 is a view of an electronic device including an interconnect structure according to another example embodiment;

FIG. 6 is a view of an electronic device including an interconnect structure according to another example embodiment;

FIG. 7 is a view of an electronic device including an interconnect structure according to another example embodiment;

FIG. 8 is a view of an electronic device including an interconnect structure according to another example embodiment; and

FIG. 9 is a view of an electronic device including an interconnect structure according to another example embodiment.

FIG. 10 is a view of an electronic device including an interconnect structure according to another example embodiment;

FIG. 11 is a view of an electronic device including an interconnect structure according to another example embodiment;

FIG. 12 is a view of an electronic device including an interconnect structure according to another example embodiment;

FIG. 13 shows Raman spectra of nanocrystalline graphenes grown on conductive metals;

FIG. 14 is a view of an experimental result showing a change in resistance before and after annealing when nanocrystalline graphene is capped on Cu, when no capping is performed on Cu, and when TaN is capped on Cu;

FIGS. 15A and 15B are views of Atomic Force Microscope (AFM) images showing changes in topography before and after annealing when no capping is performed on Ru;

FIGS. 16A and 16B are views of AFM images showing changes in topography before and after annealing when nanocrystalline graphene is capped on Ru;

FIGS. 17A to 17C are views of a state before and after annealing of a bonding structure of TiN and Ru when no capping is performed on Ru; and

FIGS. 18A to 18C are views of a state before and after annealing of a bonding structure of TiN and Ru when nanocrystalline graphene is capped on Ru.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. The same reference numerals refer to the same elements throughout. In the drawings, the sizes of constituent elements may be exaggerated for clarity. Furthermore, when an element is referred to as being “on” or “above” another element, it may be directly on the other element, or intervening elements may also be present. Moreover, the materials constituting each layer in the following embodiments are merely examples, and other materials may be used.

FIG. 1 is a view of an electronic device 100 including an interconnect structure 120 according to an example embodiment.

Referring to FIG. 1, the electronic device 100 includes a substrate 110 and the interconnect structure 120 provided on the substrate 110. The interconnect structure 120 may include a dielectric layer 121, a conductive wiring 125, a barrier layer 126, and a cap layer 127.

The substrate 110 may include a semiconductor substrate. For example, the substrate 110 may include a group IV semiconductor material, a group III/V semiconductor compound, or a group II/VI semiconductor compound. As a specific example, the substrate 110 may include silicon (Si), germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), SiGeC, a Ge alloy, gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and the like. However, this is merely an example and various semiconductor materials may be used for the substrate 110.

The substrate 110 may include a single layer or multiple layers in which different materials are stacked. The substrate 110 may include, for example, a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (SGOI) substrate. In addition, the substrate 110 may include a non-doped semiconductor material or a doped semiconductor material.

The substrate 110 may include at least one of a semiconductor device (not shown), an interconnect structure, a conductive wiring, and the like. The semiconductor device may include at least one of, for example, a transistor, a capacitor, a diode, and a resistor. However, inventive concepts are not limited thereto.

The dielectric layer 121 is formed on the substrate 110. The dielectric layer 121 may have a single layer structure or a multi-layer structure in which different materials are stacked. The dielectric layer 121 may include a dielectric material used in a typical semiconductor manufacturing process. For example, the dielectric layer 121 may include silicon oxide, nitride, silicon nitride, silicon carbide, silicate, and the like. However, this is merely an example and various dielectric materials may be used as the dielectric layer 121. The dielectric layer 121 may also include an organic dielectric material.

At least one trench 121 a may be formed in the dielectric layer 121 to a certain depth. The at least one trench 121 a may be formed not to reach the substrate 110 or to reach the substrate 110. Two trenches 121 a are formed in the dielectric layer 121 in FIG. 1, wherein one of the trenches 121 a is formed not to reach the substrate 110 and the other is formed to reach the substrate 110.

The conductive wiring 125 is provided so as to fill the inside of the trench 121 a. The conductive wiring 125 may include a metal or a metal alloy having excellent electrical conductivity. For example, the conductive wiring 125 may include at least one of copper (Cu), ruthenium (Ru), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), chromium (Cr), Rh, Ir, Pd, or Os, or an alloy thereof, or a combination thereof. However, inventive concepts are not limited thereto, and various metals may be used as the conductive wiring 125.

A barrier layer 126 is provided on an inner wall of the trench 121 a. The barrier layer 126 may be provided to cover the conductive wiring 125 between the dielectric layer 121 and the conductive wiring 125. In more detail, the barrier layer 126 may be provided on the inner wall of the trench 121 a so as to cover a side surface and a lower surface of the conductive wiring 125. An upper surface of the conductive wiring 125 may be exposed by the barrier layer 126. The barrier layer 126 may limit and/or prevent the diffusion of materials constituting the conductive wiring 125. Meanwhile, the barrier layer 126 may additionally serve as an adhesive layer between the dielectric layer 121 and the conductive wiring 125.

The barrier layer 126 may include a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The barrier layer 126 may include, for example, a metal, a metal alloy, or metal nitride. As a specific example, the barrier layer 126 may include Ta, Ti, Ru, RuTa, IrTa, W, titanium nitride (TiN), tantalum nitride (TaN), ruthenium nitride (RuN), IrTaN, TiSiN, Co, Mn, MnO, or WN. However, this is merely an example and various materials may be used as the barrier layer 126. For example, the barrier layer 126 may include nanocrystalline graphene, which will be described later below.

The cap layer 127 is provided on the upper surface of the conductive wiring 125 that fills the trench 121 a. The cap layer 127 is provided so as to cover the exposed upper surface of the conductive wiring 125. The cap layer 127 may have an edge perpendicular to an edge of the conductive wiring 125.

The cap layer 127 provided on the upper surface of the conductive wiring 125 may include nanocrystalline graphene. The cap layer 127 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene. For example, the nanocrystalline graphene may include crystals having a nanoscale size, specifically a size of 100 nm or less. When the cap layer 127 made of nanocrystalline graphene is provided on the upper surface of the conductive wiring 125 as described later below, electrical resistance of the conductive wiring 125 may be reduced, thereby improving electromigration resistance.

Hereinafter, intrinsic graphene, nanocrystalline graphene, and an amorphous carbon layer will be specifically described and compared with each other.

FIGS. 2A to 2C are example views of Raman spectrums representing typical crystalline graphene, nanocrystalline graphene, and an amorphous carbon layer, respectively. The ratio of carbon having an sp² bonding structure to total carbon described later below may be obtained, for example, by an X-ray photoelectron spectroscopy (XPS) analysis, and the content of hydrogen may be obtained by composition analysis of Rutherford backscattering spectroscopy.

FIG. 2A is an example view of a Raman spectrum representing intrinsic graphene.

Referring to FIG. 2A, for the intrinsic graphene, which is crystalline graphene, the ratio of D peak intensity to G peak intensity may be, for example, less than about 0.1, and the ratio of 2D peak intensity to the G peak intensity may be, for example, greater than about 2. The intrinsic graphene may include crystals of a size greater than about 100 nm.

In the intrinsic graphene, the ratio of carbon having an sp² bonding structure to total carbon may be almost 100%. Further, the intrinsic graphene may include very little hydrogen. In addition, density of the intrinsic graphene may be, for example, about 2.1 g/cc, and sheet resistance of the intrinsic graphene may be, for example, about 100 to 300 Ohm/sq.

FIG. 2B is an example view of a Raman spectrum representing nanocrystalline graphene.

Referring to FIG. 2B, for the nanocrystalline graphene, the ratio of D peak intensity to G peak intensity may be, for example, less than about 2.1, and the ratio of 2D peak intensity to the G peak intensity may be, for example, greater than about 0.1. A full width at half maximum (FWHM) of a D peak may be, for example, about 25 to 120 cm⁻¹.

The nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, for example, crystals having a size of about 0.5 nm to 100 nm. In the nanocrystalline graphene, the ratio of carbon having an sp² bonding structure to total carbon may be, for example, about 50% to about 99%. The nanocrystalline graphene may include, for example, hydrogen of about 1 atomic percent (at %) to about 20 at %. Also, density of the nanocrystalline graphene may be, for example, about 1.6 g/cc to 2.1 g/cc, and sheet resistance of the nanocrystalline graphene may be, for example, greater than about 1000 Ohm/sq.

FIG. 2C is an example view of a Raman spectrum representing an amorphous carbon layer.

Referring to FIG. 2C, in the amorphous carbon layer, an FWHM of a D peak may be, for example, greater than about 120 cm−1. In the amorphous carbon layer, the ratio of carbon having an sp2 bonding structure to total carbon may be, for example, about 30% to about 50%. The amorphous carbon layer may include, for example, hydrogen having a ratio greater than about 20 at %.

In recent years, the size of semiconductor devices is gradually decreasing for the high integration of semiconductor devices. Therefore, the line width of a conductive wiring may be reduced. However, when the line width of the conductive wiring is reduced, current density in the conductive wiring is increased, and as a result, electrical resistance of the conductive wiring increases. Such an increase in the electrical resistance causes electromigration phenomena, so that defects occur in the conductive wiring, thereby damaging the conductive wiring. The electromigration phenomena refer to the movement of a material due to the continuous movement of ions in a conductor caused by the transfer of momentum between conductive electrons and atomic nuclei in a metal.

When the cap layer 127 covering the upper surface of the conductive wiring 125 is made of nanocrystalline graphene, as in the present embodiment, the electrical resistance of the conductive wiring 125 may be reduced. As a specific example, when a cap layer made of Co is provided on the upper surface of a copper wiring, electrical resistance of the copper wiring may be reduced by about 4% compared with a case where the cap layer is not provided on the upper surface of the copper wiring. On the contrary, when a cap layer made of nanocrystalline graphene is provided on the upper surface of a copper wiring, electrical resistance of the copper wiring may be reduced by about 10% compared with a case where the cap layer is not provided on the upper surface of the copper wiring.

As such, the electrical resistance of the conductive wiring 125 may be reduced by providing the cap layer 127 made of nanocrystalline graphene on the upper surface of the conductive wiring 125, and electromigration resistance may be improved. Therefore, it is possible to reduce the occurrence of defects in the conductive wiring 125, thereby limiting and/or preventing the conductive wiring 125 from being damaged.

FIGS. 3A to 3C are example views of a method of manufacturing the electronic device 100 including the interconnect structure 120 shown in FIG. 1.

Referring to FIG. 3A, the dielectric layer 121 including at least one trench 121 a is formed on the substrate 110. In more detail, first, the dielectric layer 121 is formed on the substrate 110. The dielectric layer 121 may be formed using a deposition process used in a general semiconductor manufacturing process, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), spin coating, or the like.

The substrate 110 may include a semiconductor substrate. For example, the substrate 110 may include a Group IV semiconductor material, a Group III/V semiconductor compound, or a Group II/VI semiconductor compound. The substrate 110 may include a single layer or multiple layers in which different materials are stacked. Furthermore, the substrate 110 may include, for example, a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (SGOI) substrate. In addition, the substrate 110 may include a non-doped semiconductor material or a doped semiconductor material.

The substrate 110 may include at least one of a semiconductor device (not shown), an interconnect structure, a conductive wiring, and the like. For example, the semiconductor device may include at least one of a transistor, a capacitor, a diode, and a resistor, but is not limited thereto.

The dielectric layer 121 may include a dielectric material used in a typical semiconductor manufacturing process. For example, the dielectric layer 121 may include silicon oxide, nitride, silicon nitride, silicon carbide, silicate, and the like. However, this is merely an example and various dielectric materials may be used as the dielectric layer 121. The dielectric layer 121 may also include an organic dielectric material. The dielectric layer 121 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked.

Next, at least one trench 121 a is formed in the dielectric layer 121 to a certain depth. The at least one trench 121 a may be formed by, for example, a photolithography process and an etching process. The at least one trench 121 a may be formed not to reach the substrate 110 or to reach the substrate 110. Two trenches 121 a are formed in the dielectric layer 121 in FIG. 3A, wherein one of the trenches 121 a is formed not to reach the substrate 110 and the other is formed to reach the substrate 110.

Referring to FIG. 3B, the conductive wiring 125 and the barrier layer 126 are formed in at least one trench 121 a of the dielectric layer 121. First, the barrier layer 126 is formed so as to cover a surface of the dielectric layer 121. Here, the barrier layer 126 may be formed by a deposition process used in a general semiconductor manufacturing process. The barrier layer 126 may include, for example, a metal, a metal alloy, metal nitride, or nanocrystalline graphene. However, inventive concepts are not limited thereto. The barrier layer 126 may include a single layer structure or a multi-layer structure in which different materials are stacked.

Next, the conductive wiring 125 is formed on a surface of the barrier layer 126 so as to fill the inside of the at least one trench 121 a. The conductive wiring 125 may be formed by CVD, PECVD, physical vapor deposition (PVD), electroplating, chemical solution deposition, electroless plating, or the like. Meanwhile, when the conductive wiring 125 is formed by electroplating, a plating seed layer (not shown) for promoting electroplating may be formed on the surface of the barrier layer 126 before the conductive wiring 125 is formed. Such a plating seed layer may include, for example, Cu, a Cu alloy, iridium (Ir), Ir alloy, Ru, or a Ru alloy, but this is merely an example.

The conductive wiring 125 may include a metal or a metal alloy having excellent electrical conductivity. For example, the conductive wiring 125 may include Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, Rh, Ir, Pd, or Os, an alloy thereof, or at least one of combinations thereof. However, inventive concepts are not limited thereto, and various metals may be used as the conductive wiring 125.

Subsequently, as shown in FIG. 3B, the upper surface of the dielectric layer 121, the upper surface of the barrier layer 126, and the upper surface of the conductive wiring 125 are processed to be flush through a planarization process. Here, the planarization process may include, for example, a chemical mechanical polishing (CMP) process or a grinding process, but is not limited thereto.

Referring to FIG. 3C, the cap layer 127 including nanocrystalline graphene is provided on the upper surface of the conductive wiring 125. The cap layer 127 may be formed to cover an exposed upper surface of the conductive wiring 125. Here, the cap layer 127 including nanocrystalline graphene may have a single layer structure or a multi-layer structure.

As described above, the nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene, for example, crystals having a size of about 100 nm or less, in more detail, crystals having a size of about 0.5 nm to 100 nm. In the nanocrystalline graphene, the ratio of carbon having an sp² bonding structure to total carbon may be, for example, about 50% to about 99%. The nanocrystalline graphene may include, for example, hydrogen of about 1 at % to about 20 at %. Also, density of the nanocrystalline graphene may be, for example, about 1.6 g/cc to 2.1 g/cc, and sheet resistance of the nanocrystalline graphene may be, for example, greater than about 1000 Ohm/sq.

The cap layer 127 may be formed on the upper surface of the conductive wiring 125 by growing nanocrystalline graphene through a deposition process such as CVD or PECVD. As a specific example, the cap layer 127 may be formed by growing nanocrystalline graphene on the upper surface of the conductive wiring 125 at a relatively low temperature, for example, at a temperature of about 700° C. or less, using PECVD. The cap layer 127 may also be formed by transferring nanocrystalline graphene to the upper surface of the conductive wiring 125 in addition to the deposition process.

In the above, the case where the dielectric layer 121 including the trench 121 a is formed on the substrate 100 and then the conductive wiring 125 is formed inside the trench 121 a has been described. However, the present disclosure is not limited thereto, and the conductive layer 125 may be formed by depositing a conductive material on the substrate 100 and patterning the conductive material, and then the dielectric layer 121 may be formed around the conductive wiring 125. In this case, the trench 121 a having a shape corresponding to the conductive wiring 125 may be formed on the dielectric layer 121.

FIG. 4 is a view of an electronic device 200 including an interconnect structure 220 according to another example embodiment. Hereinafter, different content from the above-described embodiments will be mainly described.

Referring to FIG. 4, the electronic device 200 includes the substrate 110 and the interconnect structure 220 provided on the substrate 110. The interconnect structure 220 may include the dielectric layer 121, the conductive wiring 125, the barrier layer 126, and the cap layer 227.

Since descriptions of the substrate 110 and the dielectric layer 121 are already provided above, repeated descriptions thereof will not be given herein. At least one trench 121 a may be formed in the dielectric layer 121 to a certain depth. The conductive wiring 125 is provided so as to fill the inside of the trench 121 a. The conductive wiring 125 may include a metal or a metal alloy having excellent electrical conductivity, for example, Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, Rh, Ir, Pd, or Os, an alloy thereof, or at least one of combinations thereof. However, this is merely an example. The barrier layer 126 is provided on an inner wall of the trench 121 a. The barrier layer 126 may be provided to cover the conductive wiring 125 between the dielectric layer 121 and the conductive wiring 125. In more detail, the barrier layer 126 may be provided on the inner wall of the trench 121 a so as to cover the side surface and the lower surface of the conductive wiring 125. An upper surface of the conductive wiring 125 may be exposed by the barrier layer 126.

A cap layer 227 is provided on the upper surface of the conductive wiring 125 and an upper surface of the barrier layer 126. In more detail, the cap layer 227 is provided so as to cover the exposed upper surface of the conductive wiring 125 and an exposed upper surface of the barrier layer 126.

The cap layer 227 may include nanocrystalline graphene. As described above, the nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene, for example, crystals having a size of about 100 nm or less. Since the nanocrystalline graphene has been described in detail in the above-described embodiments, repeated descriptions thereof will not be given herein.

FIG. 5 is a view of an electronic device 300 including an interconnect structure 320 according to another example embodiment. Hereinafter, different content from the above-described embodiments will be mainly described.

Referring to FIG. 5, the electronic device 300 includes the substrate 110 and the interconnect structure 320 provided on the substrate 110. The interconnect structure 320 may include the dielectric layer 121, the conductive wiring 125, the barrier layer 126, and a cap layer 327.

Since descriptions of the substrate 110 and the dielectric layer 121 are already provided above, repeated descriptions thereof will not be given herein. At least one trench 121 a may be formed in the dielectric layer 121 to a certain depth. The conductive wiring 125 is provided so as to fill the inside of the trench 121 a. The barrier layer 126 is provided on the inner wall of the trench 121 a. In more detail, the barrier layer 126 may be provided on the inner wall of the trench 121 a so as to cover the side surface and the lower surface of the conductive wiring 125. An upper surface of the conductive wiring 125 may be exposed by the barrier layer 126.

The cap layer 327 is provided on the upper surface of the conductive wiring 125, the upper surface of the barrier layer 126, and a partial upper surface of the dielectric layer 121. In more detail, the cap layer 227 is provided so as to cover the exposed upper surface of the conductive wiring 125, an exposed upper surface of the barrier layer 126, and an exposed upper surface of the dielectric layer 121 around the barrier layer 126.

The cap layer 327 may include nanocrystalline graphene. As described above, the nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene, for example, crystals having a size of about 100 nm or less. Since the nanocrystalline graphene has been described in detail in the above-described embodiments, repeated descriptions thereof will not be given herein.

FIG. 6 is a view of an electronic device 400 including an interconnect structure 420 according to another example embodiment. Hereinafter, different content from the above-described embodiments will be mainly described.

Referring to FIG. 6, the electronic device 400 includes the substrate 110 and the interconnect structure 420 provided on the substrate 110. The interconnect structure 420 may include the dielectric layer 121, the conductive wiring 125, the barrier layer 126, and a cap layer 427.

Since descriptions of the substrate 110 and the dielectric layer 121 are already provided above, repeated descriptions thereof will not be given herein. At least one trench 121 a may be formed in the dielectric layer 121 to a certain depth. The conductive wiring 125 is provided so as to fill the inside of the trench 121 a. The barrier layer 126 is provided on the inner wall of the trench 121 a. In more detail, the barrier layer 126 may be provided on the inner wall of the trench 121 a so as to cover the side surface and the lower surface of the conductive wiring 125. An upper surface of the conductive wiring 125 may be exposed by the barrier layer 126.

A metal-containing layer 428 and a cap layer 427 are sequentially formed on the upper surface of the conductive wiring 125. The metal-containing layer 428 may promote growth and formation of nanocrystalline graphene constituting the cap layer 427.

The metal-containing layer 428 may include a metal or a metal alloy having better corrosion resistance or oxidation resistance than a material constituting the conductive wiring 125. For example, the metal-containing layer 428 may include ruthenium (Ru), Ir, platinum (Pt), cobalt (Co), rhodium (Rh), CoW, CoWP, or an alloy thereof. However, this is merely an example. The metal-containing layer 428 may have a single layer structure or a multi-layer structure. The metal-containing layer 428 may be selectively formed on the upper surface of the conductive wiring 125 by, for example, CVD, PECVD, atomic layer deposition (ALD), or the like.

The cap layer 427 is formed on an upper surface of the metal-containing layer 428. The cap layer 427 may include nanocrystalline graphene. As described above, the nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene, for example, crystals having a size of about 100 nm or less. Since the nanocrystalline graphene has been described in detail in the above-described embodiments, repeated descriptions thereof will not be given herein. As described above, the cap layer 427 may be formed more effectively on the upper surface of the metal-containing layer 428 since the metal-containing layer 428 may promote the growth and formation of the nanocrystalline graphene.

FIG. 7 is a view of an electronic device 500 including an interconnect structure 520 according to another example embodiment.

Referring to FIG. 7, the electronic device 500 includes the substrate 110 and the interconnect structure 520 provided on the substrate 110. The interconnect structure 520 may include the dielectric layer 121, a conductive wiring 525, a barrier layer 526, and a cap layer 527.

The substrate 110 may include a semiconductor substrate. For example, the substrate 110 may include a Group IV semiconductor material, a Group III/V semiconductor compound, or a Group II/VI semiconductor compound. However, inventive concepts are not limited thereto. The substrate 110 may include a single layer or multiple layers in which different materials are stacked. In addition, the substrate 110 may include a non-doped semiconductor material or a doped semiconductor material. The substrate 110 may include at least one of a semiconductor device (not shown), an interconnect structure, a conductive wiring, and the like. For example, the semiconductor device may include at least one of a transistor, a capacitor, a diode, and a resistor, but is not limited thereto.

The dielectric layer 121 is formed on the substrate 110. The dielectric layer 121 may have a single layer structure or a multi-layer structure in which different materials are stacked. The dielectric layer 121 may include a dielectric material used in a typical semiconductor manufacturing process. For example, the dielectric layer 121 may include an inorganic dielectric material or an organic dielectric material.

At least one trench 121 a may be formed in the dielectric layer 121 to a certain depth. The at least one trench 121 a may be formed not to reach the substrate 110 or to reach the substrate 110. Two trenches 121 a are formed in the dielectric layer 121 in FIG. 7, wherein one of the trenches 121 a is formed not to reach the substrate 110 and the other is formed to reach the substrate 110.

The conductive wiring 525 is provided so as to fill the inside of the trench 121 a. The conductive wiring 525 may include a metal or a metal alloy having excellent electrical conductivity. For example, the conductive wiring 525 may include Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, Rh, Ir, Pd, or Os, an alloy thereof, or at least one of combinations thereof. However, inventive concepts are not limited thereto, and various metals may be used as the conductive wiring 525. The cap layer 527 is provided so as to cover the entire surface of the conductive wiring 525. The cap layer 527 may include first and second cap layers 527 a and 527 b. The first cap layer 527 a may cover an upper surface of the conductive wiring 525 and an upper surface of the second cap layer 527 b, and the second cap layer 527 b may cover outer surfaces, that is, a side surface and a lower surface, of the conductive wiring 525 in the trench 121 a.

The cap layer 527 may include nanocrystalline graphene. The cap layer 527 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene, for example, crystals having a size of about 100 nm or less.

As such, the electrical resistance of the conductive wiring 525 may be reduced by providing the cap layer 527 made of nanocrystalline graphene on the entire surface of the conductive wiring 125, and thus electromigration resistance may be improved. In more detail, the first cap layer 527 a may increase electromigration resistance which may occur on the upper surface of the conductive wiring 525, and the second cap layer 527 b may be provided inside the trench 121 a to increase electromigration resistance which may occur in the side surface and the lower surface of the conductive wiring 525. The second cap layer 527 b may also serve as a diffusion barrier for limiting and/or preventing the diffusion of materials constituting the conductive wiring 525.

The barrier layer 526 is provided to cover the second cap layer 527 b inside the trench 121 a. In more detail, the barrier layer 526 may be provided to cover a side surface and a lower surface of the second cap layer 527 b. The barrier layer 526 may limit and/or prevent the diffusion of materials constituting the conductive wiring 525. The barrier layer 526 may include a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The barrier layer 526 may include, for example, a metal, a metal alloy, metal nitride, or nanocrystalline graphene. As a specific example, the barrier layer 126 may include Ta, Ti, Ru, RuTa, IrTa, W, TaN, TiN, RuN, TuTaN, IrTaN, TiSiN, Co, Mn, MnO, or WN. However, this is merely an example and various materials may be used as the barrier layer 526.

In the present embodiment, the second cap layer 527 b capable of serving as a diffusion barrier is provided between the conductive wiring 525 and the barrier layer 526 to reduce the thickness or the number of layers required for the barrier layer 526.

Meanwhile, FIG. 7 shows an example in which the first cap layer 527 a covers the upper surface of the conductive wiring 525 and the upper surface of the second cap layer 527 b. However, the first cap layer 527 a may be formed to cover only the upper surface of the conductive wiring 525. The first cap layer 527 a may also be formed to cover the upper surface of the conductive wiring 525, the upper surface of the second cap layer 527 b, and the upper surface of the dielectric layer 121 around the second cap layer 527 b.

FIG. 8 is a view of an electronic device 600 including an interconnect structure 620 according to another example embodiment. Hereinafter, different content from the above-described embodiments will be mainly described.

Referring to FIG. 8, the electronic device 600 includes the substrate 110 and the interconnect structure 620 provided on the substrate 110. The interconnect structure 620 may include the dielectric layer 121, a conductive wiring 625, a barrier layer 626, and a cap layer 627.

The substrate 110 may include a semiconductor substrate. The substrate 110 may include a single layer or multiple layers in which different materials are stacked. In addition, the substrate 110 may include a non-doped semiconductor material or a doped semiconductor material. The substrate 110 may include at least one of a semiconductor device (not shown), an interconnect structure, a conductive wiring, and the like.

The dielectric layer 121 is formed on the substrate 110. The dielectric layer 121 may have a single layer structure or a multi-layer structure in which different materials are stacked. The dielectric layer 121 may include a dielectric material used in a typical semiconductor manufacturing process. For example, the dielectric layer 121 may include an inorganic dielectric material or an organic dielectric material. At least one trench 121 a may be formed in the dielectric layer 121 to a certain depth. The at least one trench 121 a may be formed not to reach the substrate 110 or to reach the substrate 110.

The conductive wiring 625 is provided so as to fill the inside of the trench 121 a. The conductive wiring 625 may include a metal or a metal alloy having excellent electrical conductivity. For example, the conductive wiring 625 may include Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, Rh, Ir, Pd, or Os, an alloy thereof, or at least one of combinations thereof. However, this is merely an example.

The barrier layer 626 is provided to cover outer surfaces, that is, a side surface and a lower surface, of the conductive wiring 625 in the trench 121 a. An upper surface of the conductive wiring 625 may be exposed by the barrier layer 626. The barrier layer 626 may limit and/or prevent the diffusion of materials constituting the conductive wiring 625. The barrier layer 626 may include a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The barrier layer 626 may include, for example, a metal, a metal alloy, metal nitride, or nanocrystalline graphene.

The cap layer 627 is provided so as to cover the conductive wiring 625 and the barrier layer 626. The cap layer 627 may include first and second cap layers 627 a and 627 b. The first cap layer 627 a may cover the upper surface of the conductive wiring 625, an upper surface of the barrier layer 626, and an upper surface of the second cap layer 627 b, and the second cap layer 627 b may cover outer surfaces, that is, a side surface and a lower surface, of the barrier layer 626 in the trench 121 a.

The cap layer 627 may include nanocrystalline graphene. The cap layer 627 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene, for example, crystals having a size of about 100 nm or less.

The first cap layer 627 a may increase electromigration resistance which may occur on the upper surface of the conductive wiring 625, and the second cap layer 627 b may be provided inside the trench 121 a to increase electromigration resistance which may occur in the side surface and the lower surface of the conductive wiring 625. The second cap layer 627 b may also serve as a diffusion barrier for limiting and/or preventing the diffusion of materials constituting the conductive wiring 625.

In the present embodiment, the second cap layer 627 b capable of serving as a barrier is provided on the side surface and the lower surface of the barrier layer 626 to reduce the thickness or the number of layers required for the barrier layer 626.

Meanwhile, FIG. 8 shows an example in which the first cap layer 627 a covers the upper surface of the conductive wiring 625, the upper surface of the barrier layer 626, and the upper surface of the second cap layer 627 b. However, the first cap layer 627 a may also be formed to cover the upper surface of the conductive wiring 625 or to cover the upper surface of the conductive wiring 625 and the upper surface of the barrier layer 626. The first cap layer 627 a may also be formed to cover the upper surface of the conductive wiring 625, the upper surface of the barrier layer 626, and the upper surface of the dielectric layer 121 around the second cap layer 627 b.

FIG. 9 is a view of an electronic device including an interconnect structure 720 according to another example embodiment. Hereinafter, different content from the above-described embodiments will be mainly described.

Referring to FIG. 9, the electronic device 700 includes the substrate 110 and the interconnect structure 720 provided on the substrate 110. The interconnect structure 720 may include the dielectric layer 121, a conductive wiring 725, a barrier layer 726, and a cap layer 727.

The substrate 110 is provided with the dielectric layer 121. At least one trench 121 a may be formed in the dielectric layer 121 to a certain depth. The at least one trench 121 a may be formed not to reach the substrate 110 or to reach the substrate 110.

The conductive wiring 725 is provided so as to fill the inside of the trench 121 a. The conductive wiring 725 may include a metal or a metal alloy having excellent electrical conductivity. The barrier layer 726 is provided so as to cover the entire surface (that is, an upper surface, a side surface, and a lower surface) of the conductive wiring 725. The barrier layer 726 may include, for example, a metal, a metal alloy, metal nitride, or nanocrystalline graphene.

The cap layer 727 is provided so as to cover the barrier layer 726. The cap layer 727 may include first and second cap layers 727 a and 727 b. The first cap layer 727 a may cover an upper surface of the barrier layer 726 and an upper surface of the second cap layer 727 b, and the second cap layer 727 b may cover outer surfaces, that is, a side surface and a lower surface, of the barrier layer 726 in the trench 121 a.

The cap layer 727 may include nanocrystalline graphene. The cap layer 727 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked. The nanocrystalline graphene may include crystals that are smaller in size than intrinsic graphene, which is typical crystalline graphene, for example, crystals having a size of about 100 nm or less.

The first and second cap layers 727 a and 727 b may increase electromigration resistance which may occur in the conductive wiring 725. The first and second cap layers 727 a and 727 b may also serve as a diffusion barrier for limiting and/or preventing the diffusion of materials constituting the conductive wiring 725. Accordingly, the thickness or the number of layers required for the barrier layer 726 may be reduced.

According to the above example embodiments, the electrical resistance of a conductive wiring may be reduced by providing a cap layer including nanocrystalline graphene in the conductive wiring, thereby improving electromigration resistance. As a result, it is possible to reduce the occurrence of defects in the conductive wiring, thereby limiting and/or preventing the conductive wiring from being damaged.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.

While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

FIG. 10 is a view of an electronic device 800 including an interconnect structure 820 according to another example embodiment.

Referring to FIG. 10, the substrate 110 is provided with the dielectric layer 121 including at least one trench 121 a, and the conductive wiring 825 is provided to fill the interior of the trench 121 a. In addition, the barrier layers 826 are provided on both sides and the bottom of the conductive wiring 825. The barrier layer 826 may be further provided on the top of the conductive wiring 825.

The cap layer 827 is provided below the conductive wiring 825. The cap layer 827 may be provided to cover a lower surface of the conductive wiring 825. In this case, the cap layer 827 may be provided between the lower surface of the conductive wiring 825 and the barrier layer 826. The cap layer 827 may include nanocrystalline graphene. In the above, the case in which the cap layer 827 is provided inside the barrier layer 826 has been described, but the cap layer 827 may be provided outside the barrier layer 826. FIG. 11 shows an electronic device 900 including an interconnect structure 920 according to another example embodiment.

Referring to FIG. 11, the substrate 110 is provided with the dielectric layer 121 including at least one trench 121 a, and the conductive wiring 925 is provided to fill the interior of the trench 121 a. In addition, the barrier layers 926 are provided on both sides and the bottom of the conductive wiring 925. The barrier layer 926 may be further provided on the top of the conductive wiring 925.

The cap layer 927 is provided on both sides of the conductive wiring 925. The cap layer 927 may be provided to cover both side surfaces of the conductive wiring 925. In this case, the cap layer 927 may be provided between the both side surfaces of the conductive wiring 925 and the barrier layer 926. The cap layer 927 may include nanocrystalline graphene. In the above, the case in which the cap layer 927 is provided inside the barrier layer 926 has been described, but the cap layer 927 may be provided outside the barrier layer 926. FIG. 12 shows an electronic device 1000 including an interconnect structure 1020 according to another example embodiment.

Referring to FIG. 12, the substrate 110 is provided with the dielectric layer 121 including at least one trench 121 a, and the conductive wiring 1025 is provided to fill the interior of the trench 121 a. In addition, the barrier layers 1026 are provided on both sides and the bottom of the conductive wiring 1025. The barrier layer 1026 may be further provided on the top of the conductive wiring 1025.

The cap layer 1027 is provided on the top and both sides of the conductive wiring 1025. The cap layer 1027 may include a first cap layer 1027 a covering an upper surface of the conductive wiring 1025 and a second cap layer 1027 b covering both side surfaces of the conductive wiring 1025. Here, the second cap layer 1027 b may be provided between the both side surfaces of the conductive wiring 1025 and the barrier layer 1026. The cap layer 1027 may include nanocrystalline graphene. In the above, the case where the second cap layer 1027 b is provided inside the barrier layer 1026 has been described, but the second cap layer 1027 b may be provided outside the barrier layer 1026.

FIG. 13 shows Raman spectra of nanocrystalline graphenes grown on conductive metals. In more detail, FIG. 13 shows Raman spectra of nanocrystalline graphene grown by plasma chemical vapor deposition (PECVD) on Cu, Pt, Ir, Rh, and Ru.

Each of the Raman spectra shown in FIG. 13 has a shape similar to the Raman spectrum shown in FIG. 2B, and accordingly, it can be seen that graphene grown on each of Cu, Pt, Ir, Rh, and Ru is nanocrystalline graphene.

FIG. 14 is a view of an experimental result showing a change in resistance before and after annealing when nanocrystalline graphene is capped on Cu, when no capping is performed on Cu, and when TaN is capped on Cu.

In FIG. 14, “▪” indicates a change in resistance before and after annealing when annealing is performed on Cu capped with nanocrystalline graphene, “●” indicates a change in resistance before and after annealing when annealing (annealing) is performed on uncapped Cu, and “▾” indicates a change in resistance before and after annealing when annealing is performed on Cu capped with TaN. “Nc-G” means nanocrystalline graphene and is the same in the following.

Referring to FIG. 14, when nanocrystalline graphene is capped on Cu, it can be seen that the resistance is reduced by about 5% to 10% compared to the case where no capping is performed on Cu, and the thinner the thickness of Cu, the greater the resistance decrease. In addition, when annealing is performed on uncapped Cu, the resistance decrease is small, and when TaN is capped on Cu, the resistance increases.

[Table 1] shows experimental results showing a change in resistance (Rs) before and after annealing in the case of not capping Ru (“Ru”) and in the case of capping nanocrystalline graphene on Ru (“nc-G/Ru”).

TABLE 1 Ru nc-G/Ru Rs (ohm/sq) Rs (ohm/sq) Reduced Reduced Thickness Before After Resistance Thickness Before After Resistance (nm) Annealing Annealing (%) (nm) Annealing Annealing (%) 20 14.9 933 −6162 20 9.8 7.3 25.5

Referring to [Table 1], before annealing, when nanocrystalline graphene is capped on Ru, the resistance decreases from 14.9 to 9.8 compared to when no capping is performed on Ru. In addition, when no capping is performed on Ru, the resistance after annealing increases significantly compared to the resistance before annealing, whereas when nanocrystalline graphene is capped on Ru, the resistance after annealing decreases compared to the resistance before annealing.

[Table 2] shows experimental results showing a change in resistance (Rs) before and after annealing in the case of not capping Rh (“Rh”) and in the case of capping nanocrystalline graphene on Rh (“nc-G/Rh”).

TABLE 2 Rh nc-G/Rh Rs (ohm/sq) Rs (ohm/sq) Reduced Reduced Thickness Before After Resistance Thickness Before After Resistance (nm) Annealing Annealing (%) (nm) Annealing Annealing (%) 8 20.88 151.06 −623.57 8 18.18 12.55 30.97 16.4 6.38 6.56 −2.85 16.4 6.589 6.39 3.028 32 2.72 2.97 −9.03 32 2.66 2.43 8.87

Referring to [Table 2], when no capping is performed on Cu, it can be seen that that the resistance after annealing is increased compared to the resistance before annealing, whereas when nanocrystalline graphene is capped on Rh, the resistance after annealing is decreased compared to the resistance before annealing.

FIGS. 15A and 15B are views of AFM images showing changes in topography before and after annealing when no capping is performed on Ru. Annealing is performed at 950° C. for 90 seconds.

FIG. 15A shows an AFM image before annealing, and FIG. 15B shows an AFM image after annealing. Referring to FIGS. 15A and 15B, it can be seen that deformation before and after annealing is large when Ru is not capped.

FIGS. 16A and 16B are AFM images showing changes in topography before and after annealing when capping nanocrystalline graphene on Ru.

FIG. 16A shows an AFM image before annealing, and FIG. 16B shows an AFM image after annealing. Referring to FIGS. 16A and 16B, when nanocrystalline graphene is capped on Ru, deformation before and after annealing is small. That is, in the case of capping nanocrystalline graphene on Ru, the shape of Ru changes little even after annealing proceeds. Therefore, capping nanocrystalline graphene on a conductive wiring may reduce deformation of a conductive wiring due to heat.

When annealing is performed on a bonding structure of a platinum metal (e.g., Ru, Rh, Pd, Os, Ir, or Pt) and a metal (e.g., Ti or TiN) having a standard oxidation-reduction potential of 0 or less, oxidation, nitration, hillock, or migration of the metal having a standard oxidation-reduction potential of 0 or less may occur by oxygen or nitrogen. These problems may be prevented by capping nanocrystalline graphene on the bonding structure.

FIGS. 17A to 17C show a state before and after annealing of a bonding structure of Ru (a platinum metal) and TiN (a metal having a standard oxidation-reduction potential of 0 or less) when no capping is performed on Ru.

FIG. 17A shows a state before annealing of a bonding structure of Ru 12 and TiN 11. Referring to FIG. 17A, the TiN 11 and the Ru 12 are sequentially formed on an SiO₂ layer 10. FIG. 17B shows a state after annealing is performed on the structure shown in FIG. 17A. Referring to FIG. 17B, Ru 12′ and TiN 11′ are sequentially formed on an SiO₂ layer 10′. FIG. 17C shows a Transmission Electron Microscope (TEM) image of the structure of FIG. 17B.

Referring to FIGS. 17A to 17C, when annealing is performed on the structure shown in FIG. 17A, as shown in FIG. 17B, it can be seen that the TiN 11 below the Ru 12 moves to the top of the Ru 12 by oxygen or nitrogen. In addition, as shown in FIG. 17C, it can be seen that Ru is largely deformed by annealing.

FIGS. 18A to 18C are views of a state before and after annealing of a bonding structure of TiN and Ru when capping nanocrystalline graphene on Ru.

FIG. 18A shows a state before annealing of a bonding structure of Ru 22 and TiN 21. Referring to FIG. 18A, the TiN 21 and the Ru 22 are sequentially formed on an SiO₂ layer 20, and nanocrystalline graphene 23 is capped on an upper surface of Ru 22. FIG. 18B shows a state after annealing is performed on the structure shown in FIG. 17A. Referring to FIG. 18B, in the same manner as in FIG. 18A, TiN 21′, Ru 22′, and nanocrystalline graphene 23′ are sequentially formed on the SiO₂ layer 20′. FIG. 18C shows a TEM image of the structure of FIG. 18B.

Referring to FIGS. 18A to 18C, when the nanocrystalline graphene 23 is capped on the Ru 22 as shown in FIG. 18A, it can be seen that the structures before and after annealing remain the same as shown in FIG. 18B. Also, as shown in FIG. 18C, it can be seen that Ru is less deformed even after annealing.

As described above, when nanocrystalline graphene is capped on a bonding structure of a conductive wiring including, for example, Ru, Rh, Pd, Os, Ir, and Pt and a barrier layer including Ti, TiN, and the like, a structure of the bonding structure may be maintained even when annealing is performed, and deformation of the conductive wiring may also be reduced. 

What is claimed is:
 1. An interconnect structure comprising: a dielectric layer comprising at least one trench; a conductive wiring filling an inside of the at least one trench; and a cap layer on at least one surface of the conductive wiring, the cap layer comprising nanocrystalline graphene, the nanocrystalline graphene comprising nano-sized crystals.
 2. The interconnect structure of claim 1, wherein the conductive wiring comprises one of a metal, a metal alloy, and a combination thereof.
 3. The interconnect structure of claim 2, wherein the metal may comprises at least one of Cu, Ru, Al, Co, W, Mo, Ti, Ta, Ni, Pt, Cr, Rh, Ir, Pd, and Os.
 4. The interconnect structure of claim 1, further comprising: a barrier layer provided on the conductive wiring in the at least one trench.
 5. The interconnect structure of claim 4, wherein the barrier layer comprises a metal, a metal alloy, metal nitride, or nanocrystalline graphene, and has a single layer structure or a multi-layer structure in which a plurality of layers are stacked.
 6. The interconnect structure of claim 4, wherein the barrier layer comprises Ta, Ti, Ru, RuTa, IrTa, W, TaN, TiN, RuN, IrTaN, TiSiN, Co, Mn, MnO, or WN.
 7. The interconnect structure of claim 4, wherein the conductive wiring comprises a platinum metal, and the barrier layer comprises a metal having a standard oxidation-reduction potential of 0 or less.
 8. The interconnect structure of claim 4, wherein the barrier layer is provided on both sides and a bottom of the conductive wiring.
 9. The interconnect structure of claim 4, wherein the barrier layer is provided to surround the conductive wiring.
 10. The interconnect structure of claim 1, wherein the cap layer is provided on a top of the conductive wiring.
 11. The interconnect structure of claim 1, wherein the cap layer is provided on a bottom of the conductive wiring.
 12. The interconnect structure of claim 1, wherein the cap layer is provided on both sides of the conductive wiring.
 13. The interconnect structure of claim 1, wherein the cap layer is provided on a top and both sides of the conductive wiring.
 14. The interconnect structure of claim 1, wherein the cap layer is provided to surround the conductive wiring. 